1. Field of the Invention
The invention relates to design of semiconductor chips. More specifically, the invention relates to a method and an apparatus for scan chain planning in an integrated circuit.
2. Related Art
As the complexity of integrated circuits has increased, chip designers have increasingly become dependent on EDA tools (electronic design automation). In addition EDA tools have increasingly added features for testing the integrated circuits. In addition to testing the design of the integrated circuits, most EDA tools also support design for testability (DFT), which allows testing of a manufactured integrated circuit.
The most common design for testability feature is the inclusion of one or more scan chains in an integrated circuit. Scan chains are formed by tying scan elements, such as internal registers, flip-flops, and other storage elements, in series. The scan chains are then tied to external chip pins vial bonding pads. The elements in the scan chain have two functional modes. In the “mission mode”, the elements in the scan chain perform the intended logic functions of the integrated circuit. In the “test mode”, the elements of the scan chain are configured to serially receive data or to serially output the current state of the elements in the scan chain. For example, test vectors can be scanned into the scan chain, then the integrated circuit is allowed to function as intended for one or more clock cycles. Then the data from the scanned chain is read to determine whether the integrated circuit performed correctly.
As processing technology improved, the number of transistors on a single integrated circuits has increased drastically. To make use of the large number of available transistors, designers now use hierarchical design methodologies. Generally, a complex design is broken down into various layers of logic blocks. The logic blocks can be designed independently and can even be shared between different designs. The logic blocks are converted into physical blocks that are positioned in a floor plan for the integrated circuit. For example, FIG. 1 illustrates an integrated circuit design 100 with physical blocks 110, 120, 130, 140, 150, and 160. Integrated circuit design 100 would also include various glue logic (not shown) that couples the physical blocks together.
Conventionally, the various physical blocks have one or more block scan chains. For clarity, scan elements within a physical block can be referred to as a block scan element and scan elements not within a physical block can be referred to as a non-block scan element. Each block scan chain has an scan input port and a scan output port on the physical block to allow the internal block scan chains to be connected to non-block scan elements and other internal block scan chains to form one or more chip level scan chains. The number of chip level scan chains is usually selected by the chip designer based on various factors such as the number of scan elements on the chip, the number of available pins (and bonding pads) for scan chains, and the desired length of scan chains. However, the formation of the chip level scan chains is severely limited by the block scan chains both in terms of the scan input port and scan output port locations and the size of the block scan chains. Therefore, the chip level scan chains are likely to be sub-optimal even if the block scan chains are optimized. For example, the chip scan chains may be unbalanced both in terms of physical length and the number of scan elements. Hence there is a need or a method and apparatus for forming optimized chip level scan chains in hierarchical design.